Generic Silicon Photonics PDK & Design Methdology

We provide a Generic Silicon Photonics (GSiP) PDK, which is implemented in Mentor Graphics (Pyxis and Calibre) and Lumerical INTERCONNECT tools and is available for download.  The purpose of this kit is to demonstrate the functionality of a silicon photonics design flow implementation, with no restrictions to its distribution.  This kit can be adapted for different fabrication processes.  The kit provides insight into the approach taken to implement the PDK and Libraries available today, namely via OpSIS (IME) and via SiEPIC (IME, imec, EBeam).

The components of the GSiP PDK include:

  • Fabrication process parameters, mask layer table
  • Library: a small example library of components, including fibre grating couplers; waveguides, waveguide bends, and a splitter; a ring modulator; and a electrical bond pad.  
    • Component symbols for schematic capture: using the provided components and/or user-provided components, circuits can be designed at the schematic level
    • Component models: the library components include circuit models implemented in Lumerical INTERCONNECT.
    • Component physical layout: mask layout for components is implemented in fixed-layout cells (i.e., GDS, e.g., y-branch splitter) and parameterized (i.e., PCells, e.g., ring modulator). 
  • Schematic Capture: This functionality allows the designer to create a schematic of their system.  This stage of the design includes defining the connectivity between components (netlist), labelling components and ports, and choosing parameters for the PCells.
  • Circuit simulations: The schematic is exported as a netlist, and loaded in the circuit simulation tool, Lumerical INTERCONNECT. Component models are loaded from the PDK.  The connectivity is imported from the netlist.  A simulation test-bench can be defined to perform specific simulations, such as optical transmission spectrum, time domain characterization, etc.  Functionality of the system can be simulated and verified.
  • Schematic-Driven Layout (SDL):  Prior to the advent of modern EDA tools, the design focus was on drawing polygons in the physical layout.  In this approach, the components and connections are already defined, and the task is the place the components and route using the already-defined connectivity (Place and Route).  The components and connectivity are imported from the schematic and (automatically) instantiated.  The connectivity is graphically represented.  The interactive (or automated) routing tool is used to complete the metal and optical routing.
  • Waveguide routing: Electrical routing has been largely automated in the EDA tools.  In photonics designs, the tool needs additional considerations for smooth waveguide bends,  different types of waveguides,  wide low-loss waveguides for long distance routing, and waveguide crossings.
  • Design Rule Checking (DRC): Foundry supplied rules include minimum feature size, minimum spacing, inclusion and exclusion rules. Basic rules are included in this PDK for typical minimum feature sizes.  These rules are primarily concerned with what is permitted by the foundry to yield a manufacturable design.  The rule checker operates in two modes: 1) Interactive -- as the layout is constructed, the tool graphically reports the errors; this allows the designer to correct the errors immediately during layout.   Interactive checking operates on a small fraction of the layout, namely the portion of the layout that is being edited and in view.  2) Sign-off verification -- the full layout is exported and checked for errors.  An error report is provided graphically and as a list.
  • Layout Versus Schematic (LVS):  While DRC identifies errors that violate manufacturing rules, it does not identify circuit or construction errors.  LVS plays this role, by comparing the schematic and the physical layout.  It operates on the layout and identifies components and connections, creates a netlist, and compares the netlist with the original design schematic.  It identifies circuit differences, to isolate errors such as net errors (broken waveguides or metallic interconnects, disconnected optical and electrical ports, accidental crossings of interconnects), and component errors (missing components, incorrect component placed, wrong PCell parameters such as incorrect ring resonator radius).
  • Tiling: One of the manufacturability design rules concerns the density of the patterns.  In order to meet the minimum density rules, tiles are added to the layout, typically to the silicon and metal layers.  This is necessary to ensure planarity during the chemical mechanical polish (CMP) fabrication step, and also to have an etch density that is as uniform as possible leading to reduced process variability.  This GSiP does not include the tiling script as it uses a propriety language.  
  • Sub-system design example and tutorial: a 2-channel wavelength division multiplexed (WDM) optical transmitter using ring modulators. Example includes schematic, circuit simulations including optical spectra and eye diagrams, schematic-driven layout, design rule checking, layout versus schematic, and post-layout extraction.
  • Electronic / Photonic Co-Design: The GSiP PDK contains both an optical and electronic generic technology, which enables two separate chips to be co-designed.  The tools provide for data exchange between the optical and the electrical simulations.  Namely, one can design a CMOS modulator driver, and the resulting waveform can be used to drive the modulator.  Similarly, the light received by the detector is converted to a photo-current, which drives the trans-impedance amplifier.  With this approach, it is possible to design a complete CMOS-to-photonic-to-CMOS transmitter/receiver.  In this flow, both the photonic and electronic generic PDKs can be replaced with actual foundry-provided PDKs, which offers the designer flexibility in choosing which foundries are used to fabricate each of the two chips.  This design flow is presently based on data exchange, hence does not offer co-simulation of electronics and optics, hence would not be suitable for the simulation that require lock-step self-consistent simulations, such as microwave photonic electro-optical oscillators.

Download the GSiP package: Pyxis_GSiP_v0.9_r03.tgz

This design flow was presented as an invited talk at the SPIE Photonics North 2013 conference, titled "Silicon photonic circuit design methodologies".  

This presentation describes a design methodology that takes advantage of commercial electronic-design automation (EDA) tools for circuit design and layout, and integrates them with optical circuit modeling software.  The circuit-modeling tool utilizes physical-level opto-electronic simulations, and/or experimental data, to build compact models for the optical elements.  This integrated approach allows designers to study, for example, the influence of optical feedback from components such as grating couplers on the optical response of the optical circuit, taking into account the physical layout.  Such a unified methodology is essential for understanding the performance and designing for future complex silicon photonic systems.

 

Presentation slides:

    https://docs.google.com/file/d/0B8N02J5A0d9sMElNdEExNUt1T1k/view

 

 Video showing the lithography prediction simulation:

    http://www.mina.ubc.ca/ref_gfp

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